Studies are made to apply Group III-V semiconductors such as GaN and wide-gap semiconductors such as SiC to light-emitting elements, high-breakdown-voltage devices and RF devices by utilizing their own physical properties. Defects in these semiconductor materials become a problem to be overcome prior to practical implementation. For the purpose of reducing defects in a material, use of single-crystal bulk materials is more advantageous than the heteroepitaxial growth of thin film as long as the number of defects is concerned. However, these single-crystal materials are expensive. The preparation method via ion implantation/separation is employed in the manufacture of silicon-on-insulator (SOI) or silicon-on-sapphire (SOS), for example, the method involving the steps of joining and bonding a silicon wafer (Si wafer) having hydrogen or rare gas ions implanted therein to a support substrate such as silicon wafer or sapphire wafer, heat treating the bonded substrate to cause embrittlement of the ion-implanted region in the Si wafer, separating the Si wafer at the ion-implanted region by thermal or mechanical means, for thereby transferring a Si thin film to the support substrate. With this method, a cost reduction is expectable from reuse of the wafer after transfer.
No problems arise in the bonding of SOI and SOS because the silicon wafer and sapphire wafer have a smooth surface. However, in the case of GaN wafer and SiC wafer, for example, it is very difficult to smoothen their surface to the bondable level or such smoothening needs a cost. As in the case of bonding of GaN wafer or SiC wafer, when a polycrystalline material or a suitable substrate having a polycrystalline material deposited on its surface is bonded to a substrate of different species, direct bonding is impossible because the polycrystalline material has a substantially irregular surface.
In order that a material substrate having a non-smooth or irregular surface be used in the bonding step, a study is made to deposit an amorphous material such as SiO2 or amorphous Si on the substrate surface, and to smoothen the deposited surface by chemical-mechanical polishing (CMP) or otherwise polishing to a level viable to direct bonding. See Non-Patent Document 1: O. Mountanabbir et al., Journal of Electronic Materials 39 (5), 482-488 (2010). For the deposition of SiO2 or amorphous Si, vapor phase growth methods such as plasma-enhanced chemical vapor deposition (PECVD) and low pressure chemical vapor deposition (LPCVD) are generally used. However, these methods suffer from problems of an expensive equipment and cost needed for deposition. Since the film thus deposited has a substantial surface roughness, polishing treatment must be carried out prior to the bonding step. Extra steps cause another problem to the process.
As the means for depositing a film in an inexpensive manner, it is contemplated to form a spin-on-glass (SOG) layer on a rough or irregular surface. Examples of the spin-on-glass include boron phosphorus silicon glass (BPSG) and water glass. Since the SOG material contains impurities such as B, P and Na, it is difficult to use the material as a joint layer in electronic device applications using SOI, SOS, SiC, GaN or the like.
One candidate for an impurity-free SOG layer is obtained by coating a polysilazane solution and effecting heat treatment (or firing treatment) to convert the polysilazane to SiO2. Since the film resulting from conversion of polysilazane to SiO2 contains less impurities and is effective in burying an irregular pattern, studies are made to apply the film to the interlayer insulating film of devices (Patent Document 1: JP-A 2005-45230) or the gate insulating layer of organic TFT (Patent Document 2: WO 2006/019157). In these applications, however, a SiO2 film is formed at a low temperature of about 450° C. at maximum. When the film is used as the joint layer in electronic devices, the influence of components other than SiO2 and functional groups in the film becomes of concern.
Typical of the use of fired polysilazane film for bonding of substrates is an example obtained by slit coating an irregular pattern surface with polysilazane, firing the polysilazane into SiO2 and bonding it to an Si wafer (Patent Document 3: JP 4728030). In this example, the bonding process is carried out by using a substrate having steps with a height of 500 nm, slit coating the substrate with polysilazane, heating at 350° C. for conversion to SiO2, smoothening by CMP, bonding to a Si substrate having hydrogen ions implanted therein, separating the Si substrate at the ion-implanted region, and transferring a Si thin film, thus yielding a desired wafer structure. That is, polishing treatment for smoothening is essential.
As discussed above, the formation of amorphous material by CVD technique is one known example of the means for providing a smooth bonding layer on a substrate surface having a considerable roughness, but suffers from the problem of cost because an expensive equipment is necessary for film deposition, and polishing must be carried out for smoothening after the film deposition. Few studies have been made on simple means other than the CVD technique, for example, the use of SOG as the joint surface for a semiconductor device layer. With respect to the use of polysilazane as SOG, most studies are directed to the low-temperature conversion to SiO2 whereas few studies are directed to the application to the joint surface becoming a buried oxide layer of SOI. Furthermore, with respect to the means for eliminating steps on the bonding surface, an example of coating polysilazane and converting to SiO2 is known. However, since bonding follows polishing, it has not been studied whether or not a SiO2 film reduces the roughness of a bonding surface to enable bonding without a need for polishing, and whether or not the resulting SiO2 film is at a film quality level ready for use at the electronic device joint surface as the insulating film.